Week of:	Description	Notes
6/18 Week 1	Introduction, number systems, base conversions, arithmetic operations of base other than 10, BCD addition, binary codes, parity bits, binary logic and logic gates, Boolean algebra, algebraic manipulations, complements of functions, canonical forms, standard forms, (Sum of Products, Product of Sums)	1.1-1.6  2.1-2.4  HW 1
6/25 Week 2	Karnaugh map simplification Systematic Boolean simplification, prime implicants, tabular methods, don't cares, NAND and NOR 2-level and multi-level realization, parity functions, integrated circuit	2.5-2.8, Sup. 1 Mentor Tutorials Discussion: Quiz Review
6/28	QUIZ 1	HW 2
7/2 Week 3 (July 4- Holidy No class)	Combinatorial logic design methodology, analysis and design procedures, code converters, decoders, encoders, multiplexers and demultiplexers, Adders, ripple-carry adders, carry-lookahead adders, subtraction, complements, signed representations, signed arithmetic, binary multipliers, decimal arithmetic.	3.1 - 3.7 3.8-3.12 skim 3.13 3.14 Discussion:  Project Help Sessions
7/9 Week 4	Introduction to sequential circuits, latches, flip-flops, timing characteristics, sequential circuit analysis, state tables, state diagram, flip-flop input equations	4.1-4.3 Project 1 Due Discussion: Quiz Review
7/12	QUIZ 2	HW 3
7/16 Week 5	Sequential circuit design, flip flop excitation table, direct input, JK design, Asynchronous timing considerations,Verilog	4.4-4.7, n4.9 Sup. 2, Sup. 3 Discussion: Project Help Sessions
7/23 Week 6	Registers, shift registers, ripple counters, synchronous binary counters, other counters, memory organization, memory timing, three-state buffer ,	5.1-5.6, 5.8 6.1-6.4 Discussion: Quiz Review
7/26	QUIZ 3	HW 4
7/30 Week 7	ROM PLA, PAL, PLD, datapath, register transfer operations, micro-operations, mux-based and bus-based transfers, memory transfer, register files, ALU, shifter, datapath organization, datapath operations, microinstructions	6.5-6.10 7.1-7.8 Discussion: Project Help Sessions Project 2 Due
8/6 Week 8	Control word, ASM chart, hardwired control, pipelined datapath, simple computer architecture, single cycle hardwired control, multi-cycle, micro-programmed control	7.9-7.10  8.1-8.4, 8.6-8.9 Discussion: Exam Review
8/9	Final Examination

Office Hours: (Tentative)

Instructor: Leon Shohet
Office: 1441 Engineering Hall
Phone: 262-1191
Email: shohet@engr.wisc.edu
 

TA: Joe Krachey
Office: B640 Engineering Hall
Email: jkrachey@students.wisc.edu

  Office Hours and Class Times

Monday	Tuesday	Wednesday	Thursday	Friday
Office Hours: Krachey Room B640 10:30-11:30			Office Hours: Krachey Room B640 10:30-11:30
Lecture: Shohet Room 2534 11:45-1:00	Lecture: Shohet Room 2534 11:45-1:00	Lecture: Shohet Room 2534 11:45-1:00	Lecture: Shohet Room 2534 11:45-1:00
Office Hours: Shohet Room 1441 1:30-2:30	Lecture: Shohet Room 2534 1:10-2:25	Office Hours: Shohet Room 1441 1:30-2:30	Office Hours:  Shohet Room 1441                  1:30-2:30
	Office Hours: Krachey Room B640  3:00-4:00	Office Hours: Krachey Room B640 3:00-4:00	Discussion:  Krachey Room: 2540 2:35-3:35
		Discussion:  Krachey Room: 2540 4:00-5:00