Department of Electrical and Computer Engineering
University of Wisconsin - Madison
ECE/Comp Sci 352 Digital System Fundamentals
COURSE OUTLINE

Sections 1 & 2

Spring 2004
January 20, 2004

Last Updated: January 15, 2004

This is a tentative course outline. Changes will be announced in class or updated outlines will be posted on the course website for your section. Also, note that the schedule allows for 25 more minutes per week of lecture time than what is required of a four-credit course. As a consequence, some lectures will be cancelled by your lecturer and such cancellations will be announced in class or by email for individual sections.

Dates (# lectures)	Description	Notes & Assignments
Week 1 1/21, 23 (2)	Course description, conduct, outline, introduction, number systems, base conversions, arithmetic operation, binary codes, decimal codes, parity bits.	Read 1.1-1.7
		Attend Unix Tutorial (CAE).
Week 2 1/26, 28, 30 (3)	Gray codes, alphanumeric codes, arithmetic operation, binary logic, logic gates, Boolean algebra, algebraic manipulations, complements of functions, standard forms (sum of products, product of sums), Karnaugh maps.	Read 2.1-2.5 Start HW 1.
		Attend Optional Unix Tutorial (CAE).
Week 3 2/2, 4, 6 (3)	Systematic Boolean simplification using Karnaugh maps. (Quiz 1 covers up to here) Prime implicants, don't cares, more systematic Boolean simplification examples, tabular methods, multiple-level circuit optimization.	Read Supplement 1 (More Optimizations), 2.6-2.10, 3.1-3.3 Start HW 2 Sign up for Mentor Tutorial (In class or with TAs)
Week 4 2/9, 11, 13 (3) 2/12 Thursday	Other gate types, exclusive-OR operator and gates, high-impedance outputs, design concepts and automation, digital design space, design procedure technology mapping, verification, programmable implementation technologies.	Read 3.4-3.7, 4.1 - 4.5 Start HW 3 Sign up (In class or with TAs) and attend Mentor Tutorial (Room 175 CAE): Tutorials: 2/9, 10, 11, 13: 7:00-9:00 PM 2/14 (Sat): 3:00-5:00 PM
	7:15-8:30 PM, QUIZ 1 (covers through Chap. 2.5)	Location: Room 1800 EH
Week 5 2/16, 18, 20 (3)	Combinational circuits, rudimentary logic functions, decoders, encoders, multiplexors and demultiplexers, combinational function implementations, Verilog representations of combinational circuits, adders (half & full adders), ripple-carry adders, carry-lookahead adders) (Quiz 2 covers up to here).	Read 4.6-4.9, 5.1-5.2 Start HW 4 Attend Mentor Tutorial (Room 175 CAE) Tutorials: 2/16, 17, 18, 19, 20: 7:00-9:00 PM 2/21: 3:00-5:00 PM
Week 6 2/23, 25, 27 (3)	Subtraction, complements, signed representations, signed arithmetic, overflow, binary multipliers, decimal arithmetic, BCD adder, CAFÉ. Project 1 overview.	Read Supplement 2 (Decimal Arithmetic) 5.3-5.9 Start HW 5 Begin Project 1
Week 7 3/1, 3, 5 (3) 3/4 Thursday	Other arithmetic operations, Verilog behavioral descriptions Introduction to sequential circuits, latches, flip-flops, flip-flop timing	Read 6.1-6.4
	7:15-8:30 PM, QUIZ 2 (covers through Chapter 5.2 and Supplement 1)	Location: Room 1800 EH
Week 8 3/8, 10, 12 (3)	Project Part 2 overview. Sequential circuit analysis, Mealy and Moore machines, state tables, state diagrams, sequential circuit timing, simulation. (Quiz 3 covers up to here).	Read 6.5–6.9 Start HW 6
	Project Help Sessions 3/9, 10 (B555 EH, 7-8:30 pm) Note: Spring Break from 3/13 to 3/21.
Week 9 3/22, 24, 26 (3)	Project Help Sessions 3/22 (B555 EH, 6-9 pm) Project 1 due on Wednesday 3/24 in class Sequential circuit design, finding state diagrams and state tables, designing with D flip-flops and unused states, other flip-flop types, Verilog representations for sequential circuits.	Read 7.1-7.6
Week 10 3/29, 31, 4/2 (3) 3/30 Tuesday	Registers, register transfers, microoperations, shift registers, ripple counters, synchronous binary counters, other counters.	7.7-7.12 Start HW 7
	7:15-8:30 PM, QUIZ 3 (covers through Chapter 6.4 and Supplement 2)	Location: Room 1800 EH
Week 11 4/5, 7, 9 (3)	Register cell design, MUX-based and bus-based transfers, three-state buffers, serial transfers and microoperations, Verilog representations for shift registers and counters, asynchronous timing considerations (Quiz 4 covers up to here).	Read Supplement 3 (Asynchronous Sequential Circuit Concepts), 8.1-8.3 Begin Project 2
Week 12 4/12, 14, 16 (3)	Control units, algorithmic state machines (ASMs) and ASM charts, binary multiplication, hardwired control, Verilog representations of the binary multiplier, microprogrammed control.	Read 8.4-8.8, 9-1-9-2 Start HW 8
Week 13 4/19, 21, 23 (2) 4/22 Thursday	Exam reviews and Project 2 reviews. Memory definitions, random-access memory (RAM), memory timing, static RAM (SRAM) integrated circuits, arrays of SRAM ICs, Dynamic RAM (DRAM), DRAM types, Arrays of DRAM ICs.	Read 9.3-9.8 Start HW 9
	7:15-8:30 PM, Quiz 4 (covers through end of Chapter 7 and Supplement 3)	Location: Room 1800 EH
Week 14 4/26, 28, 30 (3)	Project 2 discussion Datapaths, ALU, shifter, datapath representation, datapath operations, control word.	Read 10.1-10.6 Start HW 10
	Project Help Sessions: 4/26, 27, 28 (B555 EH, 7-9pm) Project 2 due on Friday 4/30
Week 15 5/3, 5, 7 (3)	Simple instruction computer, instruction set architecture, instruction formats, single cycle computers Catch up, final exam review, course evaluation.	Read 10.7-10.8
5/14 Friday	10:05 AM - 12:05 PM FINAL EXAMINATION Covers Chapter 1 through 10.6, Supplements 1 through 3, and Quizzes 1 through 4).	Location: 1800 EH

Supplements:

Supplement 1: “More Optimization” from http://www.writphotec.com/mano/reading_supplements.html

Supplement 2: “Decimal Arithmetic” from http://www.writphotec.com/mano/reading_supplements.html

Supplement 3: “Asynchronous Sequential Circuit Concepts”.

Hard copies of the supplements are provided in the ECE352 course materials from Bob’s Copy Shop.