Department of Electrical and Computer Engineering
University of Wisconsin - Madison

 

ECE/CS 352 Digital System Fundamentals
Summer 8-Week Session 2003

 

COURSE OUTLINE

Last Updated: June 13, 2003

 

Week of:

Description

Notes

6/16
Week 1

Introduction, number systems, base conversions, arithmetic operations of base other than 10, BCD addition, binary codes, parity bits, binary logic and logic gates, Boolean algebra, algebraic manipulations, complements of functions, canonical forms, standard forms, (Sum of Products, Product of Sums)

1.1-1.6

2.1-2.4

Sup. 1 
HW 1
 

6/23
Week 2

Karnaugh map simplification Systematic Boolean simplification, prime implicants, tabular methods, don't cares, NAND and NOR 2-level and multi-level realization, parity functions, integrated circuit

2.5-2.8, Sup. 2

Mentor Tutorials
Discussion:
Quiz Review

6/26

QUIZ 1 (No discussion)

HW 2

6/30
Week 3

Combinatorial logic design methodology, analysis and design procedures, code converters, decoders, encoders, multiplexers and demultiplexers, Adders, ripple-carry adders, carry-look ahead adders, subtraction, complements, signed representations, signed arithmetic, binary multipliers, decimal arithmetic

3.1 – 3.7
3.8-3.12
skim 3.13
3.14
Discussion: 
Project Help Sessions  

7/7
Week 4

Introduction to sequential circuits, latches, flip-flops, timing characteristics, sequential circuit analysis, state tables, state diagram, flip-flop input equations

4.1-4.3
Project 1 Due
Discussion:
Quiz Review

7/10

QUIZ 2 (No discussion)

HW 3

7/14
Week 5

Sequential circuit design, flip flop excitation table, direct input, JK design, Asynchronous timing considerations, Verilog

4.4-4.7, n4.9
Sup. 3
Discussion:
Project Help Sessions

7/21
Week 6

Registers, shift registers, ripple counters, synchronous binary counters, other counters, memory organization, memory timing, three-state buffer

5.1-5.6, 5.8
6.1-6.4
Discussion:
Quiz Review

 

7/24

QUIZ 3 (No discussion)

HW 4

 

7/28
Week 7

ROM PLA, PAL, PLD, datapath, register transfer operations, micro-operations, mux-based and bus-based transfers, memory transfer, register files, ALU, shifter, datapath organization, datapath operations, microinstructions

6.5-6.10
7.1-7.8, Sup. 4
Discussion:
Project Help Sessions
Project 2 Due

8/4
Week 8

Control word, ASM chart, hardwired control, pipelined datapath, simple computer architecture, single cycle hardwired control, multi-cycle, micro-programmed control

7.9-7.10 
8.1-8.4, 8.6-8.9
Discussion:
Exam Review

8/7

Final Examination (No discussion)

 

Office Hours:

Instructor: J. Leon Shohet
Office: 1441 Engineering Hall
Phone: 262-1191
Email: shohet@engr.wisc.edu
Office Hours: 3.00 – 4.00 M, 4.00 – 5.00 T, 3.00 – 4.00 W, 3.00 – 4.00 R

 

Teaching Assistant: Ravi Murugesan

Office: B632 Engineering Hall

Phone: 265-4885

Email: ravi@cae.wisc.edu

Office Hours: 2.30 – 4.00 T, 5.00 – 6.00 W (TA will hold office hours in 3610 Engineering Hall)

Office Hours and Class Times:

Monday

Tuesday

Wednesday

Thursday

Friday

Lecture:
Shohet
Room 2540
11:45-1:00

Lecture:
Shohet
Room 2540
11:45-1:00

Lecture:
Shohet
Room 2540
11:45-1:00

Lecture:
Shohet
Room 2540
11:45-1:00

 

 

Lecture:
Shohet
Room 2540
1:10-2:25

 

Discussion: 
Room 2540
2:35-3:35

 

Office Hours:

 Shohet
Room 1441
3.00 – 4.00

Office Hours:

Ravi

Room 3610

2.30 – 4.00

Office Hours:

Shohet
Room 1441
3.00 – 4.00

 

Office Hours:

Shohet
Room 1441
3.00 – 4.00

 

 

 

Office Hours:

Shohet
Room 1441
4.00 – 5.00

Discussion: 
 Room 2540
4:00-5:00

 

 

 

 

Office Hours:

Ravi

Room 3610

5.00 – 6.00