Dates (# lectures)

Description

Notes & Assignments

Week 1
9/2-9/8 (2)

Introduction, number systems, base conversions, arithmetic operations for bases other than 10, binary codes

1.1-1.4
Start Homework 1

Week 2
9/9-9/15 (3)

Gray code, alphanumeric codes, parity bit, binary logic, logic gates, Boolean algebra, algebraic manipulations, complements of functions, canonical forms, standard forms (Sum of Products, Product of Sums), Karnaugh maps

Supplement 1, 1.5-1.6, 2.1-2.4

Week 3
9/16-9/22 (3)

Systematic Boolean simplification using K-maps, prime implicants, don't cares, NAND and NOR 2-level, tabular methods 

Supplement 2, 2.4-2.6
Mentor Tutorial
Finish HW 1, Start HW 2

Week 4
9/23-9/29 (3)

Multi-level realization, XOR gates, parity functions, combinational circuits, combinatorial logic analysis and design procedures, code converters, decoders, encoders, multiplexers and demultiplexers

2.6 - 2.8, 3.1 - 3.10
Mentor Tutorial

Week 5
9/30-10/6 (2)

10/4 Thursday

10/5 Friday 

Adders, ripple-carry adders, carry-lookahead adders, subtraction, complements, signed representations, signed arithmetic 

3.8 - 3.10
Mentor Tutorial
Finish HW 2, Start HW 3

7:15-8:45 PM, QUIZ 1

No Class

Location: TBD

Week 6
10/7-10/13 (3)

10/8 Monday  

Overflow, binary multipliers, decimal arithmetic, HDL representation, introduction to sequential circuits.

3.10-3.14, 4-1

Begin Project 1

Week 7
10/14-10/20 (3)

Latches, flip-flops, timing characteristics, sequential circuit analysis, state tables

4.2-4.4, Supplement 3
Finish HW 3, Start HW 4

Week 8
10/21- 10/27 (2)
10/25 Thursday

10/26 Friday

State diagrams, flip-flop input equations, analysis examples

4.4

7:15-8:45 PM, QUIZ 2

No Class 

Location: TBD 

Week 9
10/28-11/3 (3)

Sequential circuit design. flip-flop excitation table, HDL representations

4.5-4.7, 4.9
Finish HW 4, Start HW 5

Project Help Sessions: 10/29,10/30,10/31,11/1, 7-9 PM(B555 EH) 

Week 10
11/4 - 11/10 (3)

11/5 Monday

Registers, shift registers, ripple counters, synchronous binary counters, other counters, HDL representations

5.1-5.6, 5.8

Submit Project 1
Begin Project 2 

Week 11
11/11 - 11/17 (2)

11/15 Thursday
11/16 Friday

Memory organization, and memory timing

6.1-6.5
Finish HW 5, Start HW 6

7:15-8:45 PM, QUIZ 3

No Class

Location: TBD 

Week 12
11/18- 11/24 (2)

11/22-11/25

ROM, PLA, PAL, PLD. Asynchronous timing considerations. Micro-operations, register transfer operations, three-state buffers, MUX-based and bus-based transfers, memory transfer

6.6-6.8, Supplement 4, 7.1-7.5

 Thanksgiving Recess

Week 13
11/25 - 12/1 (3)

Register files, ALU, shifter, datapath organization. datapath operations, microinstructions, control word, control unit, ASM chart

7.6-7.10, 8.1-8.4
Finish HW 6, Start HW 7

Project Help Sessions: 11/26,11/27, 1/28,11/29,7-9 PM(B555 EH)

Week 14
12/2-12/8 (3)

12/3 Monday

12/6 Thursday
12/7 Friday

Hardwired control, multiple-cycle microprogrammed control, HDL descriptions of control

8.6-8.7

 Submit Project 2

7:15-8:45 PM, QUIZ 4

No Class 

Location: TBD 

Week 15
12/9-12/14 (3)

Single cycle hardwired control, final exam review, evaluations

8.8-8.9
Finish HW 7, Start HW 8

12/20 Thursday

7:25 PM -9:25 PM - FINAL EXAMINATION

Location: TBD