Department of Electrical and Computer Engineering
University of Wisconsin - Madison
ECE/Comp Sci 352 Digital System Fundamentals
COURSE OUTLINE

Sections 1 & 2

Fall 2003-2004
August 25, 2003

Last Updated: December 9, 2003

This is a tentative course outline. Changes will be announced in class or updated outlines will be posted on the course website for your section. Also, note that the schedule allows for 25 more minutes per week of lecture time than what is required of a four credit course. As a consequence, some lectures will be cancelled by your lecturer and such cancellations will be announced in class or by email for individual sections. .

Dates (# lectures)	Description	Notes & Assignments
Week 1 9/3, 5 (2)	About the course description, conduct, outline, introduction, number systems. Base conversions, arithmetic operation, binary codes	Read 1.1-1.4 and Supplement 1 Gray codes (from Course Materials)
		Attend Unix Tutorial (CAE).
Week 2 9/8, 10, 12 (3)	Codes (binary codes, Gray code, alphanumeric codes), arithmetic operation for bases other than 10. Parity bit, binary logic, logic gates, Boolean algebra, algebraic manipulations More algebraic manipulations, complements of functions, canonical forms, standard forms (Sum of Products, Product of Sums), Karnaugh maps	Read 1.5-1.6, 2.1-2.4, Start HW 1.
		Attend Optional Unix Tutorial (CAE).
Week 3 9/15, 17, 19 (3)	Systematic Boolean simplification using K-maps, (Quiz 1 covers upto here), prime implicants, don't cares, 5-Variable K-maps More Systematic Boolrean Simplification Examples, Tabular methods	Supplement 2, Ch. 2.4-2.8 Start HW 2 Sign up for Mentor Tutorial (In class or with TAs)
Week 4 9/22, 24, 26 (3) 9/25 Thursday	NAND and NOR 2-level, AND-OR, AND-NOR, NAND-NAND, NAND-AND, OR-AND, OR-NAND, NOR-NOR, NOR-OR realization from K-map, multi-level realization, XOR gates, parity functions, propagational delay Combinational circuits, combinatorial logic analysis and design procedures, code converters	3.1 - 3.8 Sign up(In class or with TAs) and attend Mentor Tutorial (Room 175 CAE) Tuts: 9/22, 9/23, 9/26: 7:00-9:00 PM 9/27(Sat): 3:00-5:00 PM
	7:15-8:30 PM, QUIZ 1 (covered through Chap. 2.4, Supp. 1)	Location: Room 1800 EH
Week 5 9/29, 10/1, 3 (3)	Decoders, encoders, multiplexers and demultiplexers Adders (half & full adders), ripple-carry adders, carry-lookahead adders) , (Quiz 2 covers upto here), Subtraction, complements, decimal arithmetic	3.8 - 3.11 Start HW 3 Attend Mentor Tutorial (Room 175 CAE) Tutorials: 9/29, 9/30, 10/1, 10/2: 7:00-9:00 PM 10/4: 11:00-1:00 and 3:00-5:00 PM
Week 6 10/6, 8, 10 (3)	Signed representations, signed arithmetic, overflow, binary multipliers Project 1 overview, BCD adder, CAFE Verilog representation, Introduction to sequential circuits	3.11 – 3.14 4.1 - 4.2 Begin Project 1
Week 7 10/13,15,17 (3) 10/16 Thursday	Introduction to sequential circuits Latches and Flip-Flops Flip-Flops, timing characteristics (Supplement 3)	4.2 - 4.3 Start HW 4
	7:15-8:30 PM, QUIZ 2(covers supplement 2 and chapters through sec. 3.8)	Location: Room 1800 EH
Week 8 10/20, 22, 24 (3)	Huffman model, Mealy and Moore machine, Project Part 2 overview. Sequential circuit analysis, state tables, state diagram, analysis examples, (Quiz 3 covers upto here), Sequential circuit design	4.3-4.7
	Project Help Sessions 10/21, 22, 23 (B555 EH, 7-9pm)
Week 9 10/27, 29, 10/31 (3)	Project 1 due on Monday 10/27 in class Sequential circuit design. flip-flop excitation table, timing consideration (supplement 3) Verilog representations.	4.7, 4.9, Supplement 3
Week 10 11/3, 5, 7 (3) 11/6 Thursday	Sequential circuit design Flip-flop input equations, verilog representations Registers, shift registers, ripple counters, synchronous binary counters	4.7, 4.9, 5.1-5.6, 5.8, Start HW 5
	7:15-8:30 PM, QUIZ 3 (covers supplement 3 and through Chap.4.4)	Location: Room 1800 EH
Week 11 11/10, 12, 14 (3)	Other counters, HDL representations. Asynchronous timing considerations. (Quiz43 covers upto here), Micro-operations, register transfer operations, three-state buffers, MUX-based and bus-based transfers, memory transfer	5.8 Supplement 4, Ch. 7.1-7.5 Start HW 6, Begin Project 2
Week 12 11/17, 19, 21 (3)	Register files, ALU, shifter, datapath organization. datapath operations, microinstructions, control word, control unit,	7.6-7.9,
Week 13 11/24, 11/26 (2) 11/25 TUESDAY	Exam reviews and Project 2 reviews microinstructions, control word, control unit	7.9-7.10 Start HW 7
	7:15-8:30 PM, Quiz 4 (covers Supplement 4 and through end of Chapter 5)	Location: Room 1800 EH
Week 14 12/1, 3, 5 (3)	Project 2 discussion Hardwired control, multiple-cycle microprogrammed control, ASM chart, binary multiplication	8.1-8.4, 8.6 Start HW 8,
	Project Help Sessions: 12/1, 2, 3 (B555 EH, 7-9pm) Project 2 due on Friday 12/5
Week 15 12/8, 12/10. 12/12 (3)	HDL descriptions of control, simple computer architecture, instruction format, single cycle hardware control, Memory organization, and memory timing, ROM, PLA, PAL Catch up, final exam review, course evaluation	6.1-6.8
12/16 Tuesday	12:25 - 2:25 PM FINAL EXAMINATION Covers Chapter 1 through 8 and Supplements 1 through 4. (You are responsible for all materials, Quiz 1 through Quiz 4, Ch 7, Ch 8.1-8.4, 8.6 and Chapter 6.1-6.8, ).	Location: 1800 EH